1. Field of the Invention
The present invention generally relates to an analog to digital (A/D) converter wherein the number of inverting elements through which a pulse signal is transmitted is changed in dependent on an analog voltage signal to convert the analog voltage signal into a digital value corresponding to the number of inverting elements.
2. Description of Related Art
An A/D converter is, for example, disclosed in Japanese Patent No. 3064644, and a block diagram of this converter is shown in FIG. 1. As shown in FIG. 1, an A/D converter 1 formed as an integrated circuit (IC) chip has a pulse phase difference encoding circuit 2 and a control circuit 4. The circuit 4 periodically generates two control signals PA and PB having a fixed phase difference from each other. The phase difference is defined as a period of time Ts (hereinafter, called sampling time Ts) from a level rise time of the signal PA to a level rise time of the signal PB. The circuit 2 produces digital data indicating an analog value of a voltage by using the signals PA and PB. The circuit 2 has a pulse transit circuit 10, a counter 12, a latch 14, a pulse selector 16, an encoder 18, and a signal processor 19.
The circuit 10 has an odd number of elements composed of an NAND gate 101 and an even number of inverters 102. The number of inverters 102 is, for example, set at 14 in the circuit 10. The gate 101 and the inverters 102 are connected with one another in a ring shape so as to form a ring oscillator. The gate 101 receives the signal PA of the circuit 4 and an output of the inverter 102 disposed at the former stage of the gate 101. When the gate 101 receives the signal PA set at low level, the gate 101 always outputs a high level signal to the gate 101 disposed at the latter stage of the gate 101. Therefore, a signal output from each of the gate 101 and inverters 102 is maintained at a low or high level. In contrast, when the gate 101 receives the signal PA set at high level, the gate 101 outputs a high level signal in response to a low level signal of the former inverter 102 or outputs a low level signal in response to a high level signal of the former inverter 102. Therefore, the gate 101 acts as a starting inverter, and a level of a pulse signal transmitted through the gate 101 and inverters 102 is changed each time the signal passes through the gate 101 or one inverter 102. Further, because the total number of the gate 101 and inverters 102 is odd, each of the gate 101 and inverters 102 changes a level of the pulse signal every reception of the pulse signal. Therefore, in response to a level rise of the signal PA, the gate 101 and inverters 102 starts changing levels of input signals one after another as if a pulse signal starts going around the gate 101 and inverters 102 while changing its level in each of the gate 101 and inverters 102. That is, the pulse signal is repeatedly circulated in the circuit 10 while changing its level at each element, so that the circuit 10 acts as a pulse circulation circuit.
The counter 12 increments a counting number each time a level of an output of the inverter 102 disposed at the former stage of the gate 101 is changed or inverted and outputs first digital data indicating the counting number. The first digital data is expressed by binary digits. The counting number denotes the number of times in the circulation of the pulse signal and is called a circulation number in this specification.
The latch 14 holds an updated first digital data output from the counter 12 and outputs the first digital data when receiving the signal PB set at high level from the circuit 4. Therefore, in response to a level rise of the signal PB, the latch 14 outputs the first digital data to the processor 19. The first digital data indicates the circulation number of the pulse signal within the sampling time Ts.
The selector 16 receives the output signals of the gate 101 and inverters 102, detects a transit position of the pulse signal from the levels of the output signals and outputs a position signal indicating the transit position when receiving the signal PB set at high level from the circuit 4. More specifically, the gate 101 and inverters 102 change levels of those output signals one after another every circulation of the pulse signal. When a first element of the circuit 10 changes the level of the pulse signal at a certain time, this level is the same as that of the output signal of a second element placed just at the latter stage of the first element at this certain time. Therefore, when detecting two signals of the same level from two particular elements adjacent to each other at a detection time, the selector 16 recognizes that the pulse signal is positioned at the particular element placed at the former stage of the other particular element at the detection time. Therefore, the position signal indicates a transit position at which the pulse signal is placed at the detection time. The transit position is indicated by the total number of elements placed between the gate 101 and the particular element. The selector 16 outputs the transit position to the encoder 18 at a detection time the signal PB is changed to a high level.
The encoder 18 produces second digital data from the position signal of the encoder 18 such that the second digital data indicates the transit position at the detection time. The second digital data is expressed by binary digits.
The processor 19 receives the first digital data of the latch 14 and the second digital data of the encoder 18, and produces final digital data DO1 from the first and second digital data such that the final digital data DO1 indicates the number of elements through which the pulse signal passes within the sampling time Ts. More specifically, the number of elements to be indicated by the final digital data DO1 is equal to a sum of the second digital data and a product of the number of elements in the circuit 10 and the circulation number. The processor 19 produces combined digital data from the combination of the second digital data placed at lower bits (for example, four lower bits) of the combined digital data and the first digital data placed at upper bits of the combined digital data by shifting the first digital data by N bits (for example, four bits) to the upper side. Then, to compensate a difference between 2N and the total number of elements in the circuit 10, the processor 19 adds the first digital data to the combined digital data, so that the final digital data DO1 is produced. Therefore, the A/D converter can output the final digital data DO1 indicating the number of elements through which the pulse signal passes within the sampling time Ts.
Further, an analog voltage signal Vin is applied from a terminal 2a to each of the gate 101 and inverters 102 of the circuit 10 as a power source voltage to drive the gate 101 and inverters 102. Each element of the circuit 10 inverts an input signal into an output signal in an inversion operation time Ti which is changed in dependent on a level of the voltage signal Vin. Further, the number of elements through which the pulse signal passes within the sampling time Ts is determined by dividing the sampling time Ts by the inversion operation time Ti. Therefore, the final digital data DO1 is changed in dependent on the time Ti. In other words, the final digital data DO1 corresponding to the voltage signal Vin is obtained in the A/D converter, so that a digital value indicating the level of the signal Vin can be obtained from the data DO1.
Further, because the A/D converter periodically outputs the data DO1 in response to the signals PA and PB of the fixed phase difference, a change in the voltage signal Vin can be indicated by a change in the data DO1. Accordingly, the A/D converter can convert the analog voltage signal Vin changing with time into digital data expressed by binary digits.
However, a transmission speed of a pulse signal in each of the gate 101 and inverters 102 of the circuit 10 is generally very high (for example, 10 ns), so that the pulse transmission speed is easily influenced by wiring delay which is caused by resistances (hereinafter, called wiring resistance) of wires connecting elements with one another, capacitance (hereinafter, called wiring capacitance) of a capacitor formed between each wire and the ground, and parasitic capacitance between the wires disposed through an insulating layer.
As a result, elements (e.g., selector 16) subsequent to the circuit 10 are not sometimes operated as designed, thereby outputting erroneous data.
To design an A/D converter formed as an IC chip, particularly to design a pattern layout of an A/D converter, there are various restrictions in design to reduce the influence of the wiring delay. For example, wires having the same shape as one another are used to connect inverters with one another, and each inverter is formed on a portion of an insulating layer far away from a portion receiving AC coupling. Therefore, design of an A/D converter is complicated, it takes a long time for the design, and only very skillful designers are allowed to design an A/D converter. Further, an A/D converter cannot be manufactured by using a field programmable gate array (FPGA) known as one of widely-used electronic parts.